TLB miss
also: TLB fault, page table walk
A TLB miss occurs when the CPU's Translation Lookaside Buffer doesn't contain a virtual-to-physical address translation, forcing a slower lookup in the page table. This is a performance penalty because the CPU must access main memory to find the correct mapping.
The Translation Lookaside Buffer (TLB) is a small, fast hardware cache on the CPU that stores recent virtual-to-physical memory address translations. When a program accesses memory, the CPU first checks the TLB for the translation; if found (a TLB hit), the access is very fast.
A TLB miss happens when the required address translation is not cached in the TLB. The CPU must then walk the kernel's page tables in main memory to find the correct physical address. This process is much slower than a TLB hit and adds significant latency to memory access.
For example, if a program accesses memory address 0x7fffffff0000, the CPU checks its TLB. If that virtual address isn't in the TLB cache, it's a miss, and the CPU performs a page table walk (potentially multiple memory accesses) to find the mapping. Frequent TLB misses can become a performance bottleneck, especially for applications with large working sets or irregular memory access patterns.