memory barrier
also: memory fence, memory synchronization barrier
A CPU instruction that enforces ordering of memory operations, preventing the processor from reordering reads and writes across the barrier point. Essential for correct synchronization in multi-threaded and multi-processor systems.
A memory barrier (or memory fence) is a low-level CPU mechanism that guarantees the order in which memory operations are visible across processors. Modern CPUs optimize performance by reordering memory reads and writes, but this can break synchronization logic in multi-threaded code. A memory barrier forces the CPU to complete all pending memory operations before proceeding.
There are different types: a read barrier prevents reordering of read operations, a write barrier prevents reordering of writes, and a full barrier prevents reordering of both. For example, in lock-free data structures, a memory barrier ensures one thread's writes are visible to another thread before it reads a flag variable.
In Linux kernel code and multi-threaded applications, memory barriers are typically used via primitives like smp_mb(), smp_rmb(), smp_wmb() (in kernel), or higher-level constructs like mutex locks and atomic operations that implicitly include barriers. Direct use is rare in application code because synchronization libraries handle it automatically.